The present invention relates generally to data processing systems and more particularly to interrupt service enabling apparatus included therein.
In most computer systems, mechanisms are provided for providing an interrupt in response to either a watchdog timer or a real time clock time-out. The watchdog timer is utilized to indicate catastrophic conditions such as a time out without any event taking place in the computer system, whereas the real time clock is utilized to provide time outs in order to command the commencement or termination of a particular event. The interrupts produced by these mechanisms should be serviced in a set priority with respect to any other interrupts which may be included in the system. It is thus important that the interrupt priority or level be set for the particular interrupt in accordance with the importance of such interrupt in the system. Further, it is important that such priority or level be changeable under for example program control in order to easily configure the system. It is also important to be able to, for example with respect to the real time clock which may time-out for various length intervals, preset such intervals in a minimum period of time and without suspending the operation of the system during the update of such time out interval. Further, it is also important for example for debug or initialization purposes, that the real clock and watchdog timer interrupts be inhibited so that the operator may provide such initialization or debugging without constantly facing an interrupt condition. It is also particularly important to implement such interrupt mechanism with minimal logic in the data processing system.